Item Tag: IAM ELECTRONIC

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FPGA Mezzanine Card (FMC) HPC-U.FL Debug Board

TheFMC HPC-U. Signal routing includes 156 U.FL-accessible signals, with breakouts for 68 LPC LA bank lines, 48 HPC HA bank lines, 8 clock signals, and 16 differential MGT pairs. FMC HPC Debug Board with 156 U.FL Breakouts and SMA Probing.

FPGA Mezzanine Card (FMC) LPC Pin Header Board

NO SHIPPING BETWEEN 21-DEC-2020 AND 04-JAN-2021 DUE TO HOLIDAYS//--> Pin Header Board for Low-Pin Count FMC Connectors Features Low-pin count (LPC) connector Handy breakout for FMC carriers Pin headers with 2.54 mm pitch SMA connectors for high-speed data (multi gigabit transceivers) SMA connector for dedicated clock IO EEPROM for FRU information storage Small form factor Open-source hardware Applications Easy prototyping Logic Analyzer Clock Synthesizer Trigger-Generator Pattern-Generator Board-to-Board interconnections Debugging and test of digital designs Research and education with FPGAs Description The FMC pin header board was developed to make the high density FMC connector of many FPGA boards easily accessible. In many applications easily pluggable connections are required to process and check the digital signals. The use of 2.54 mm pin headers is very common. Thus, the FMC pin header board enables a variety of applications for digital signal processing and testing. The total number of 68 user signals (LAxx_P/N), 4 user clocks (CLKx_M2C_P/N) and 3 voltage rails (VADJ, 3P3V and 12PV0) from the carrier card connector are routed to the 2.54 mm pin grid on top of the adapter board. In addition, the high-speed data lanes (multi-gigabit transceivers) are easily accessible via SMA connectors on the edge of the PCB. Finally, the board allows complete interconnection of all signals from the FMC connector. The full datasheet is available at F M C H U B . C O M